2026 International Conference on Networks Computers and Communications (ICNCCom 2026)

Deploying full-precision multilayer perceptron (MLP) controllers for DC–DC converters on low-cost edge FPGAs is constrained by look-up table (LUT) and digital signal processor (DSP) budgets, particularly when fully parallel datapaths are required at the converter switching rate. We present a ternary-weight MLP for buck converter duty-cycle control in which every weight is constrained to {−1, 0, +1}, mapping the forward pass to wires, inverters, and pruned connections at synthesis time. The network is trained by behavioral cloning from a Tustin-discretized lag compensator and realized as Q15.16 synthesizable Verilog on a Xilinx Zynq-7020, with closedloop verification through System Generator co-simulation. The ternary core uses 2,830 LUTs (5.3%) and zero DSPs, versus 84,769 LUTs (159%) and 70 DSPs for an architecturally matched Q15.16 baseline that does not fit on the device. These results indicate that ternary weight quantization can enable fully parallel neural converter control on low-cost edge FPGAs.

FPGA;Neural network hardware;ternary weight quantization;DC-DC converters;buck converter control;behavioral cloning