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EPU-HEKV: Hierarchical External Memory for Bounded Active Reasoning
ID:23 View protection:Participant Only Updated time:2026-10-04 23:18:09 Views:28 Poster Presentation

Start Time:2026-10-12 08:11

Duration:1min

Session:[OP] Poster [P] Poster

Abstract
EPU-HEKV investigates hierarchical external memory for frozen large language models (LLMs) through two complementary augmentation stages. The first stage, referred to as the span/KV lane, separates historical key-value (KV) states from the compute device. During streaming prefill, KV states are organized into spans and offloaded to RAM/NVMe storage. A real attention scorer with rotary positional embeddings (RoPE) is then used to select a fixed-size working set, while the active state is strictly bounded to 1,664 tokens.
The second stage, referred to as the entity–relation–state (ERS) lane, changes the management unit from spans to entities enriched with relational and temporal-state information. Selected spans are decoded back into text, filtered to remove noise, and re-encoded into a clean prompt before subsequent processing.
On Qwen2.5-0.5B-Instruct in FP16 precision, the span/KV lane maintains a peak decode memory footprint of approximately 55 MB as the context length increases from 4K to 53K tokens, whereas the full-KV approach increases from 117.3 MB to 1,454.6 MB. The entity + re-encode + ERS pipeline achieves 90% first-pass accuracy, with 10% hallucination cases caused by insufficient evidence, using 416 context tokens, 124.22 MB of peak additional VRAM, and 0.03 MB of resident state on a 10-sample benchmark.
Overall, this work clarifies the distinction between active state, external storage, and retrieval cost. The bounded-memory guarantee applies only to the active/resident state and does not imply bounded total storage, bandwidth consumption, or retrieval computation
Keywords
External memory, KV cache, large language models (LLMs), entity–relation–state (ERS), long-context, retrieval
Speaker
Van Dinh Vu
Electric Power University

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Important Dates
  • Conference date

    10-11

    2026

    -

    10-14

    2026

  • 12-30 2025

    Presentation submission deadline

  • 09-28 2026

    Early Bird Registration

  • 10-14 2026

    Draft paper submission deadline

  • 10-15 2026

    Registration deadline

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Posts and Telecommunications Institute of Technology

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