2026 ASIAN Conference on Communication and Networks (ASIANComNet 2026)

Machine-learning-based network intrusion detection systems (NIDSs) are attractive for Internet of Things (IoT) gateways, but software-only inference on embedded CPUs can constrain latency and host-side processing headroom. This paper presents a CPU--FPGA coprocessor workflow for real-time, flow-based NIDS inference on the AMD Kria KV260 platform. Two dense neural classifiers, denoted DNN-1 and DNN-2, are trained on IoT-23 flow features, converted to 16-bit fixed-point HLS designs using \texttt{hls4ml} and Vitis, and integrated as AXI-controlled FPGA inference IPs. The evaluation compares FPGA execution with integer TensorFlow Lite inference on a BeagleBone Black Arm Cortex-A8 host and on the Kria KV260 Arm Cortex-A53 host. The FPGA implementations preserve high classification accuracy, achieving 99.62\% for DNN-1 and 99.93\% for DNN-2, close to their PC-side references of 99.65\% and 99.98\%, respectively. They also reduce average latency to 26.561 and 17.890~$\mu$s/sample. These values correspond to 11.17$\times$/5.69$\times$ speedups for DNN-1 and 9.54$\times$/4.94$\times$ speedups for DNN-2 over the BeagleBone Black/Kria KV260 CPU baselines. Resource results reveal complementary deployment points: DNN-1 uses 3.31\% of LUTs, 2.04\% of registers, 0.35\% of BRAM tiles, and no DSP slices, whereas DNN-2 uses 209 DSP slices for faster dense-layer arithmetic. The results show that CPU--FPGA offloading can provide microsecond-scale IDS inference with a tunable trade-off among accuracy, latency, software-control overhead, and FPGA resources.

intrusion detection systems,hls4ml,FPGA,Edge Security,IoT-23,Kria KV260